AL Tech 8CH Instrukcja Użytkownika Pobierz pdf (Strona 14)

LTC2424/LTC2428

As long as the voltage on the V

pin is maintained within

the –0.3V to (V

+ 0.3V) absolute maximum operating

range, a conversion result is generated for any input value

from –0.125 • V

REF

to 1.125 • V

REF

For input voltages

greater than 1.125 • V

REF

, the conversion result is clamped

to the value corresponding to 1.125 • V

REF

. For input

voltages below –0.125 • V

REF

, the conversion result is

clamped to the value corresponding to –0.125 • V

REF

APPLICATIONS INFORMATION

WUU

Channel Selection

Typically, CSADC and CSMUX are tied together or CSADC

is inverted and drives CSMUX. SCK and CLK are tied

together and driven with a common clock signal. During

channel selection, CSMUX is HIGH. Data is shifted into the

pin on the rising edge of CLK, see Figure 4. Table 3

shows the bit combinations for channel selection. In order

to enable the multiplexer output, CSMUX must be pulled

Figure 4. Typical Data Input/Output Timing

EOC “0”

SDO

SCK/CLK

CSMUX/CSADC

MSB LSB

D2EN D1 D0

EXTSIG

BIT 22BIT 23 BIT 0

24248 F04

Hi-Z

DON’T CARE

CONV

Hi-Z

Table 2. LTC2424/LTC2428 Output Data Format

Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 Bit 15 … Bit 0

Input Voltage EOC DMY SIG EXR MSB LSB

> 9/8 • V

REF

0 01100 0 11...1

9/8 • V

REF

0 01100 0 11...1

REF

+ 1LSB 0 01100 0 00...0

REF

0 01011 1 11...1

3/4V

REF

+ 1LSB 0 01011 0 00...0

3/4V

REF

0 01010 1 11...1

1/2V

REF

+ 1LSB 0 01010 0 00...0

1/2V

REF

0 01001 1 11...1

1/4V

REF

+ 1LSB 0 01001 0 00...0

1/4V

REF

0 01000 1 11...1

–

0 0 1/0* 0 0 0 0 0 0 ... 0

–1LSB 0 0 0111 1 11...1

–1/8 • V

REF

0 00111 1 00...0

< –1/8 • V

REF

0 00111 1 00...0

*The sign bit changes state during the 0 code.

1 2 ... 9 10 11 12 13 14 15 16 17 18 19 ... 35 36

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